1. Field of the Invention
This application relates generally to pipelined packet processors, and, more specifically, to packet processors that normally process each packet by performing a fixed number of processing cycles on the packet as it passes through the processing pipeline.
2. Related Art
In conventional packet processing systems employing a pipelined packet processing architecture, a packet processor performs a fixed number of processing cycles on each of the packets as they pass through the pipeline. If a packet requires less than the fixed number of processing cycles, the remaining cycles are consumed with “no operation” (NOP) cycles. Packet processing is simplified as each of the packets is processed through the pipeline in order, and there is little or no chance that the packets will get out of order.
A problem with the conventional approach is there is no satisfactory way of handling the situation where a packet requires more than the fixed number of processing cycles. Either the extra processing cycles are avoided so that system can output packets at line rate—in which case processing of the packet is not completed, resulting in a non-optimal or incorrect processing decision for the packet—or else the fixed number of processing cycles applied to each packet is increased to the maximum number of cycles any of the packets will require—resulting in many more of the packets being burdened with extra cycles that are wasted and filled with NOP operations.